1. Field of the Invention
The present invention generally relates to lead-on-chip semiconductor device packages, and more particularly, to a method and a resulting structure for attaching a semiconductor chip and the lead frame with a liquid adhesive layer.
2. Description of the Related Art
As the integration density of a semiconductor integrated circuit (IC) device increases, so does the size of the semiconductor chip. However, efforts continue in order to reduce the size of the semiconductor chip packages to meet the demand for smaller devices. To meet this need for package miniaturization, various packaging technologies have been developed. One of them is the lead-on-chip (LOC) package technology, in which a plurality of leads are disposed on and attached to an active surface of a semiconductor chip.
A primary advantage of the LOC package is that a chip mounting area, also known as a die pad or a lead frame pad, is not required since the chip is attached to the leads. Accordingly, the ratio of the size of the semiconductor chip to the size of the package is quite high. Other advantages of the LOC package include a high lead frame design flexibility, enhanced electrical performance, and the like.
A conventional LOC semiconductor device package is depicted in FIGS. 1, 2A and 2B. FIG. 1 shows a conventional LOC package 50 in a partially cut away perspective view; FIG. 2A illustrates, in an exploded perspective view, the spatial relationship between a semiconductor chip 10, an adhesive tape 30, and a lead frame 20, in the LOC package 50 shown in FIG. 1; and FIG. 2B is a more detailed view of the adhesive layer portion E of FIG. 2A.
With reference to FIGS. 1, 2A and 2B, the conventional LOC package 50 is constructed so that a plurality of inner leads 22 of the lead frame 20 are attached to an active surface of the semiconductor chip 10. Adhesion between the lead frame 20 and the semiconductor chip 10 is generally accomplished by multiple pieces of the adhesive tape 30. The adhesive tape 30 may comprise three layers, namely, a base film 32 and two adhesive layers 34, 36 formed respectively on each side of the base film 32. The base film 32 is typically a polyimide film and the adhesive layers 34, 36 are typically thermosetting epoxy resin layers. The semiconductor chip 10 has a plurality of electrode pads 12 which are centrally formed on the active surface. The inner leads 22 are spaced apart so that the central electrode pads 12 are exposed between the respective groups of inner leads 22, one on each side of the pads 12, and the inner leads 22 are electrically connected to the electrode pads 12.
Each of the inner leads 22 of the lead frame 20 is brought in close proximity to corresponding ones of the electrode pads 12, which are located along the center of the semiconductor chip 10, and thus the lead frame 20 can be electrically connected to the semiconductor chip 10 by means of short bonding wires 40.
A package body 52 is formed by encapsulants such as epoxy resins in order to protect the semiconductor chip 10, the inner leads 22, and the bonding wires 40 from hostile environments. After encapsulation, the dam bars 26 and lead frame salvage 28 shown in FIG. 2A are removed, and then outer leads 24, which extend from the package body 52 as shown in FIG. 1, are formed into an adequate shape for surface-mounting of the package 50 onto an external system board (not shown). Tie bars 27 support the package 50 during the shape-transformation of the outer leads 24.
The assembly process of the conventional LOC package 50 can be described as follows. First, a suitably sized three-layer adhesive tape 30 is positioned under the inner leads 22 of the lead frame 20, and the semiconductor chip 10 is then positioned under the three-layer adhesive tape 30. The adhesive tape 30 is attached to the inner leads 22 of the lead frame 20 by the first adhesive layer 34, and then the semiconductor chip 10 is attached to the adhesive tape 30 by the second adhesive layer 36, by applying pressure to the tape 30 at a predetermined temperature. Subsequent process steps, such as wire bonding interconnection, encapsulation, and outer lead frame forming are successively conducted.
However, the conventional LOC package suffers some drawbacks. One problem is the structure of adhesive tape itself. Since the adhesive tape consists of three layers, four interfaces exist between the semiconductor chip and the lead frame. The interfaces between two heterogeneous materials can produce thermo-mechanical stresses, and easily cause mechanical failures of the package such as cracks or delaminations. Moreover, the high water absorption property of the adhesive tape can degrade the reliability of the LOC package.
Another problem is found in the production process for the adhesive tape. The three-layer adhesive tape is made by successive sequences: first, adhesive materials are coated on one side of the base film 32 and cured to a so-called B-stage (i.e., a semi-solid state), and then also coated on the other side of the base film 32 and cured. Accordingly, the tape production process is complicated and the adhesive tape 30 is difficult to handle since it has adhesive layers on both sides thereof.
Moreover, the adhesive tape 30 contains an expensive inner polyimide film core, which consequently results in high production costs.